AdslCore

[Specification] [TitleIndex] [WordIndex]

Register offsets

Offset	Size	Meaning
`0x0000`	32 bit	ChipControl
`0x0020`	32 bit	IntStatusI
`0x0024`	32 bit	IntMaskI
`0x0028`	32 bit	IntStatusF
`0x002c`	32 bit	IntMaskF
`0x0300`	32 bit	HostMessage
`0x0f94`	32 bit	PllControl?
`0x0f98`	32 bit	ChipReset

Register descriptions

ChipControl

Value	Usage
`0x00000002`	Enable the Adsl Mips
`0x00000003`	Disable the Adsl Mips

IntStatusI

Interrupts for the interleaved port.

Mask	Usage
`0x00000020`	Set on pending messages from the phy

Note: Phy messages only assert this interrupt.

IntMaskI

IntStatusF

Interrupts for the fast port. See IntStatusI

IntMaskF

HostMessage

Mask	Usage
`0x00000001`	Notify the phy of a new message

ChipReset

Mask	Usage
`0x00000001`	put the Adsl Core into reset

Accessing the Adsl Core

Setup the PLL

if it's a BCM6338 or BCM6358
- write 0x294 to PllControl
if it's a BCM6348
- if it's revision A0
  - write 0x0073B548 to AdslPllStrap
- else
  - write 0x0053B4C2 to AdslPllStrap
- Put the Adsl Mips core into soft reset
- wait 16 us
- Clear the Adsl Mips soft reset
- write 0x8C to PllControl
don't do anything if it's a BCM6345