ChipControl

[Specification] [TitleIndex] [WordIndex]

The ChipControl core is responsible for the PLLs and GPIOs of the AdslCore and AtmCore.

Register offsets

Offset	size	Name
`0x06`	16 bit	ClockEnable
`0x28`	32 bit	SoftReset
`0x38`	32 bit	AdslPllStrap

Register descriptions

ClockEnable

Enables a core when the bit is asserted.

Core	BCM6338	BCM6345	BCM6348	BCM6358
Adsl	`0x0001`	`0x010`	`0x0001`	`0x0020`
Atm	`0x0020`	??	`0x0020`	`0x0800`

SoftReset

Puts a core into reset state as long as the bit is cleared.

Mask	Usage
`0x00000400`	Reset Adsl Mips core
`0x00000080`	Reset AtmCore
`0x00000020`	Reset AdslCore

AdslPllStrap

Configures the PLL for the Adsl Mips core

Mask	Usage
`0x00700000`	N1
`0x000f8000`	N2
`0x00007000`	M1REF
`0x00000e00`	M2REF
`0x000001c0`	M1CPU
`0x00000038`	M1BUS
`0x00000007`	M2BUS