Overview
Some bcm63xx SoCs include an 802.11 wifi core, attached through UBUS. The UBUS provides similar probe support as the Broadcom AMBA bus, but does always seem to include the same three cores, i.e. wifi shim core (the "controller" core), ChipCommon core, and the IEEE802.11 core.
Core Locations
Core |
BCM6362 |
BCM63268 |
0x10004000 |
0x10004000 |
|
0x10005000 |
0x10005000 |
|
0x10007000 |
0x10007000 |
Cores and Register Descriptions
Shim
This core provides the connection from ubus to the wifi cores, and allows control of them.
Offset |
Width |
Name |
0x0000 |
32 bit |
|
0x0004 |
32 bit |
|
0x0008 |
32 bit |
|
0x000c |
32 bit |
|
0x0010 |
32 bit |
|
0x0014 |
32 bit |
|
0x0018 |
32 bit |
|
0x001c |
32 bit |
|
0x0020 |
32 bit |
|
0x0024 |
32 bit |
|
0x0028 |
32 bit |
|
0x002c |
32 bit |
|
0x0030 |
32 bit |
|
0x0034 |
32 bit |
|
0x0038 |
32 bit |
|
0x003c |
32 bit |
ShimMisc
Bits |
Name |
Description |
[31:3] |
RESERVED |
|
[2] |
MACRO_FORCE_CLOCKS_ON |
|
[1] |
MACRO_DISABLE |
|
[0] |
MACRO_SOFT_RESET |
CcControl
The upper 16 bit are equivalent to BCMA's RESET_CTL register, while the lower 16 bit are equivalent to BCMA's IOCTL register.
Bits |
Name |
Description |
[31:17] |
RESERVED |
|
[16] |
WOC_CORE_RESET |
|
[15] |
BIST_EN |
|
[14] |
PME_EN |
|
[13:2] |
CORE_BITS |
|
[1] |
FGC |
|
[0] |
CLOCK_EN |
MacControl
The upper 16 bit are equivalent to BCMA's RESET_CTL register, while the lower 16 bit are equivalent to BCMA's IOCTL register.
Bits |
Name |
Description |
[31:17] |
RESERVED |
|
[16] |
WOC_CORE_RESET |
|
[15] |
BIST_EN |
|
[14] |
PME_EN |
|
[13:2] |
CORE_BITS |
|
[1] |
FGC |
|
[0] |
CLOCK_EN |
ShimStatus
CcStatus
The lower 16 bit are equivalent to BCMA's IOST register.
Bits |
Name |
Description |
[31:16] |
RESERVED |
|
[15] |
BIST_DONE |
|
[14] |
BIST_ERROR |
|
[13] |
GATED_CLOCK |
|
[12] |
DMA64 |
|
[11:0] |
CORE_BITS |
MacStatus
The lower 16 bit are equivalent to BCMA's IOST register.
Bits |
Name |
Description |
[31:16] |
RESERVED |
|
[15] |
BIST_DONE |
|
[14] |
BIST_ERROR |
|
[13] |
GATED_CLOCK |
|
[12] |
DMA64 |
|
[11:0] |
CORE_BITS |
ChipCommon
This is a ChipCommon core similar to the ones found on SSB and Broadcom AMBA based Wifi wifi chips/SoCs. Known revisions are 35 with a revision 6 PMU (found on BCM63268).
IEEE802.11
This is a N-PHY core similar to the ones found on SSB and Broadcom AMBA based Wifi chips/SoCs. Both BCM6262 and BCM63268 use a revision 8 N-PHY core, paired with a BCM2057 revision 8 and 12, respectively.
Controlling the Bus
Powering Up
- enable WLAN_OCP clock
- wait 10 ms
- put WLAN_SHIM_UBUS and WLAN_SHIM into reset
- wait 1 ms
- take WLAN_SHIM_UBUS and WLAN_SHIM out of reset
write MACRO_FORCE_CLOCKS_ON | MACRO_SOFT_RESET to ShimMisc
- wait 1 ms
write FGC | CLOCK_EN to MacControl
clear MACRO_SOFT_RESET in ShimMisc
clear MACRO_FORCE_CLOCKS_ON in ShimControl
clear FGC in MacControl